LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

entity div is
port(

	clk: 	in std_logic;
	clk_10k_o: out std_logic;
--	clk_sba: out std_logic;
	vdd: out std_logic

);
end div;

architecture bahave of div is

--signal
signal clk_10k: std_logic;
--signal clk_sen_100: std_logic;

signal count1: integer range 0 to 5000 := 0;
signal count2: integer range 0 to 400 := 0;


begin

q1:process(clk,clk_10k)------fenpin1   10kHz
	begin
		if rising_edge(clk) then

			if count1 < 5000 then
				count1 <= count1 +1;
			else 
				count1 <= 0;
			end if;
			
			if count1 <2500 then 
				clk_10k <= '1';
			else 
				clk_10k<= '0';
			end if;
			
		end if;
end process;

--q2:process(clk_sba_40k,clk_sen_100)------fenpin2   100Hz
--	begin
--		if rising_edge(clk_sba_40k) then
--
--			if count2 < 400 then
--				count2 <= count2 +1;
--			else 
--				count2 <= 0;
--			end if;
--			
--			if count2 < 200 then 
--				clk_sen_100 <= '1';
--			else 
--				clk_sen_100 <= '0';
--			end if;
--			
--		end if;
--end process;
    vdd<='1';
--	clk_sen<= clk_sen_100;
	clk_10k_o<= clk_10k;
end architecture;